This invention relates to the field of computerized data processing and, in particular, to a method and system for detecting error and implementing error correction during transfer of instructions from memory to a computer processor.
Embedded systems typically have a computer processor and an attached instruction memory unit that feeds instructions to be executed by the processor. The instruction unit must minimize instruction access time by providing a fast path to stored code. If instructions are not provided at the rate in which they are executed, the processor will stall, and precious cycles will be wasted waiting for code.
As embedded computer memory scales to smaller and smaller sizes, soft error rates have increased significantly. This is due in major part to the ever-increasing integration factor and decreasing feature dimensions. Unfortunately, soft errors can cause major problems in embedded systems. One example of particular concern is executing an incorrect instruction. If a soft error mutates an instruction, problems running the gamut from corrupted data to system failure can arise. None of this is acceptable in most applications. Even worse yet, the error may not be immediately obvious, making detection and correction more difficult.
An error correcting code (ECC) technique is generally used to improve data integrity. ECC involves adding a number of check bits to a data word in order to detect and correct one or more bits that have flipped while the data was stored. Unfortunately, ECC generally carries a penalty with its use. The data word and check bits must be decoded to determine if correction is needed and which bit to correct. Typically, one or more additional clock cycles are required in order to accomplish this correction, and ECC implementations generally suffer this performance penalty. However, since data integrity is crucial, the tradeoff in performance is made.
An example of a prior art ECC mechanism for accessing instructions can be found in U.S. Pat. No. 6,108,753, which employs an automatic retry when an ECC or parity error is detected. Unfortunately, this method may suffer a performance penalty because the processor cannot assume it will have a valid instruction in all cases. Therefore, the processor must wait for an error determination before deciding whether or not it can proceed.
In the error detection and correction system of U.S. Pat. No. 4,646,312, a parity error signal pauses the processor clock when asserted. During this pause, ECC correction is done on correctable data, and the processor clock is restarted when corrected data is available. Though this method improves performance execution over waiting for corrected data each cycle, the error signal must be able to halt clocks before an invalid instruction is executed. However, adding the ability to halt clocks to a processor can seriously limit pipelining within the processor, translating to extended latency and lower performance. Further, the delay from halting the clock during ECC correction of a corrupted instruction is experienced regardless of whether or not the instruction in question is actually executed. This is due to the fact that the delay occurs during retrieval.